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FAST CMOS 16-BIT BUS IDT54/74FCT16652T/AT/CT/ET IDT54/74FCT162652T/AT/CT/ET TRANSCEIVER/ REGISTERS
Integrated Device Technology, Inc.
FEATURES:
* Common features: - 0.5 MICRON CMOS Technology - High-speed, low-power CMOS replacement for ABT functions - Typical tSK(o) (Output Skew) < 250ps - Low input and output leakage 1A (max.) - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack - Extended commercial range of -40C to +85C - VCC = 5V 10% * Features for FCT16652T/AT/CT/ET: - High drive outputs (-32mA IOH, 64mA IOL) - Power off disable outputs permit "live insertion" - Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25C * Features for FCT162652T/AT/CT/ET: - Balanced Output Drivers: 24mA (commercial), 16mA (military) - Reduced system switching noise - Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25C
DESCRIPTION:
The FCT16652T/AT/CT/ET and FCT162652T/AT/CT/ET 16-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power de-
vices are organized as two independent 8-bit bus transceivers with 3-state D-type registers. For example, the xOEAB and xOEBA signals control the transceiver functions. The xSAB and xSBA control pins are provided to select either real time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real time data. A LOW input level selects real-time data and a HIGH level selects stored data. Data on the A or B data bus, or both, can be stored in the internal D-flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (xCLKAB or xCLKBA), regardless of the select or enable control pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16652T/AT/CT/ET are ideally suited for driving high capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. The FCT162652T/AT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors. The FCT162652T/AT/CT/ET are plug-in replacements for the FCT16652T/AT/CT/ET and ABT16652 for on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
1OEAB 1OEBA 1CLKBA 1SBA 1CLKAB 1SAB B REG
2OEAB 2OEBA 2CLKBA 2SBA 2CLKAB 2SAB B REG
D C
1A1 A REG 1B1
D C
2A1 A REG 2B1
D C
D C
TO 7 OTHER CHANNELS
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TO 7 OTHER CHANNELS
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-2549/8
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IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1OEAB 1CLKAB 1SAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1CLKBA 1SBA
1OEAB 1CLKAB 1SAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 E56-1
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
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1OEBA 1CLKBA 1SBA
GND
1A1 1A2
GND
1B1 1B2
GND
1A1 1A2
GND
1B1 1B2
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
VCC
2A7 2A8
VCC
2B7 2B8
VCC
2A7 2A8
VCC
2B7 2B8
GND
2SAB 2CLKAB
GND
2SBA 2CLKBA 2OEBA
GND
2SAB 2CLKAB
GND
2SBA 2CLKBA 2OEBA
2OEAB
2OEAB
SSOP/ TSSOP/TVSOP TOP VIEW
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CERPACK TOP VIEW
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IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Description Data Register A Inputs Data Register B Outputs xBx Data Register B Inputs Data Register A Outputs xCLKAB, xCLKBA Clock Pulse Inputs xSAB, xSBA xOEAB, xOEBA Output Data Source Select Inputs Output Enable Inputs
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CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. 4.5 5.5 Max. Unit 6.0 pF 8.0 pF
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Pin Names xAx
NOTE: 1. This parameter is measured at characterization but not tested.
FUNCTION TABLE(2)
Inputs xOEAB L L X H L L L L H H H xOEBA OEBA H H H H X L L L H H L xCLKAB xCLKBA H or L H or L X X X H or L H or L H or L H or L X H or L X X H or L xSAB X X X X(2) X X X X L H H
Data I/O(1) xSBA X X X X X X(2) L H X X H xAx Input Input Input Unspecified(1) Output Output Input Output xBx Input
Operation or Function Isolation Store A and B Data
Unspecified(1) Store A, Hold B Output Store A in Both Registers Input Input Input Output Output Hold A, Store B Store B in both Registers Real Time B Data to A Bus Stored B Data to A Bus Real Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus
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NOTES: 1. The data output functions may be enabled or disabled by various signals at the xOEAB or xOEBA inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition on the clocks inputs. 2. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers. 3. H = HIGH Voltage Level L = LOW Voltage Level ABSOLUTE MAXIMUM RATINGS(1) X = Don't care Symbol Description Max. = LOW-to-HIGH Transition
VTERM(2) Terminal Voltage with Respect to -0.5 to +7.0 GND VTERM(3) Terminal Voltage with Respect to -0.5 to GND VCC +0.5 TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +120
Unit V V C mA
2549 lnk 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT.
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IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS A
BUS B
BUS A
BUS B
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2549 drw 06
xOEAB
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
xOEAB
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
L
L
X
X
X
L
H
H
X
X
L
X
REAL-TIME TRANSFER BUS B TO A
REAL-TIME TRANSFER BUS A TO B
BUS A
BUS B
BUS A
BUS B
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2549 drw 08
xOEAB
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
xOEAB xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
X L L
H X H
X
X
X X X
X X X
H
L
H or L
H or L
H
H
STORAGE FROM A AND/OR B
TRANSFER STORED DATA TO A AND/OR B
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IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 10%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input Input HIGH Current (I/O Input LOW Current (I/O (3-State Output pins) (5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Min., IIN = -18mA VCC = Max., VO = GND (3)
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level pins)(5) VCC = Max. VI = VCC VI = GND VCC = Max. VO = 2.7V VO = 0.5V pins)(5) pins)(5)
Min. 2.0 -- -- -- -- -- -- -- -- -80 -- --
Typ.(2) --
-- -- -- -- -- -- -- -0.7 -140
Max.
--
Unit V V A
0.8 1 1 1 1 1 1
-1.2 -225 --
Input LOW Current (Input pins)(5) High Impedance Output Current
A V mA mV A
100 5
VCC = Max., VIN = GND or VCC
500
2549 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16652T
Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage Test Conditions(1) VCC = Max., VO = 2.5V(3) VCC = Min. VIN = VIH or VIL IOH = -3mA IOH = -12mA MIL. IOH = -15mA COM'L. IOH = -24mA MIL. IOH = -32mA COM'L.(4) VCC = Min. IOL = 48mA MIL. VIN = VIH or VIL IOL = 64mA COM'L. VCC = 0V, VIN or VO 4.5V Min. -50 2.5 2.4 2.0 -- -- Typ.(2)
--
Max.
-180
Unit mA V V V V A
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3.5 3.5 3.0 0.2 --
-- -- -- 0.55 1
VOL IOFF
Output LOW Voltage Input/Output Power Off Leakage(5)
OUTPUT DRIVE CHARACTERISTICS FOR FCT162652T
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -16mA MIL. IOH = -24mA COM'L. IOL = 16mA MIL. IOL = 24mA COM'L. Min. 60 -60 2.4 -- Typ.(2) 115 -115 3.3 0.3 Max. 200 -200 -- 0.55 Unit mA mA V V
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NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C.
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IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VIN = VCC VCC = Max. Outputs Open VIN = GND xOEAB = xOEBA=GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz (xCLKBA) 50% Duty Cycle xOEAB = xOEBA=GND One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz (xCLKBA) 50% Duty Cycle xOEAB = xOEBA=GND Sixteen Bits Toggling fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND Min. -- -- Typ.(2) 0.5 75 Max. 1.5 120 Unit mA
A/ MHz
IC
Total Power Supply Current (6)
--
0.8
1.7
mA
VIN = 3.4V VIN = GND
--
1.3
3.2
VIN = VCC VIN = GND
--
3.8
6.5 (5)
VIN = 3.4V VIN = GND
--
8.3
20.0 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
2549 tbl 08
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IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16652T/162652T Com'l. Symbol Parameter Condition(1) Min.(2) Max. Mil. Min.(2) Max. FCT16652AT/162652AT Com'l. Min.(2) Max. Mil. Min.(2) Max. Unit
Propagation Delay Bus to Bus Output Enable Time xOEAB or xOEBA to Bus Output Disable Time xOEAB or xOEBA to Bus Propagation Delay Clock to Bus Propagation Delay xSBA or xSAB to Bus Set-up Time HIGH or LOW Bus to Clock tH Hold Time HIGH or LOW Bus to Clock tW Clock Pulse Width HIGH or LOW tSK(o) Output Skew (3)
tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU
CL = 50pF RL = 500
2.0 2.0 2.0 2.0 2.0 4.0 2.0 6.0 --
9.0 14.0 9.0 9.0 11.0 -- -- -- 0.5
2.0 2.0 2.0 2.0 2.0 4.5 2.0 6.0 --
11.0 15.0 11.0 10.0 12.0 -- -- -- 0.5
2.0 2.0 2.0 2.0 2.0 2.0 1.5 5.0 --
6.3 9.8 6.3 6.3 7.7 -- -- -- 0.5
2.0 2.0 2.0 2.0 2.0 2.0 1.5 5.0 --
7.7 10.5 7.7 7.0 8.4 -- -- -- 0.5
ns ns ns ns ns ns ns ns ns
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FCT16652CT/162652CT Com'l. Symbol Parameter Condition(1) Min.(2) Max. Mil. Min.(2) Max.
FCT16652ET/162652ET Com'l. Min.(2) Max. Mil. Min.(2) Max. Unit
Propagation Delay Bus to Bus Output Enable Time xOEAB or xOEBA to Bus Output Disable Time xOEAB or xOEBA to Bus Propagation Delay Clock to Bus Propagation Delay xSBA or xSAB to Bus Set-up Time HIGH or LOW Bus to Clock tH Hold Time HIGH or LOW Bus to Clock tW Clock Pulse Width HIGH or LOW tSK(o) Output Skew (3)
tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU
CL = 50pF RL = 500
1.5 1.5 1.5 1.5 1.5 2.0 1.5 5.0 --
5.4 7.8 6.3 5.7 6.2 -- -- -- 0.5
1.5 1.5 1.5 1.5 1.5 2.0 1.5 5.0 --
6.0 8.9 7.7 6.3 7.0 -- -- -- 0.5
1.5 1.5 1.5 1.5 1.5 2.0 0.0 3.0 (4) --
3.8 4.8 4.0 3.8 4.2 -- -- -- 0.5
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns
2549 tbl 10
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested.
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IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test Open Drain Disable Low
7.0V
Switch
Closed Open
2549 lnk 07
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT
Enable Low All Other Tests
DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
2549 drw 05
SET-UP, HOLD AND RELEASE TIMES
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2549 drw 06
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
2549 drw 07
tSU
tH
PROPAGATION DELAY
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2549 drw 08
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 0V
2549 drw 09
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
tPLZ 3.5V 1.5V tPHZ 0.3V
1.5V 0V 3.5V 0.3V VOL VOH
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX FCT XXXX Device Type Temperature Range X Package X Process
Blank B PV PA PF E
Commercial MIL-STD-883, Class B Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1)
16652T Non-Inverting 16-Bit Bus Transceiver/Register 16652AT 16652CT 16652ET 162652T 162652AT 162652CT 162652ET 54 74 -55C to +125C -40C to +85C
2549 drw 14
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.
Integrated Device Technology, Inc.
2975 Stender Way, Santa Clara, CA 95054-3090 Telephone: (408) 727-6116 FAX 408-492-8674
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